Corridor of EEIC, The University of Tokyo

Programmable Gate Driver IC for Waveform Control of Power Transistors :Makoto Takamiya

Programmable Gate Driver IC for Waveform Control of Power Transistors

We are developing a programmable gate driver IC that can manipulate the gate drive current of a power transistor with a digital interface through collaboration between different fields of LSI design and power electronics. Through automatic optimum control using AI technology, we are working to reduce both loss and noise during switching of the power transistor, and to further improve the optimization method according to the operating conditions.

Degradation Estimation of Power Devices by Machine Learning of Gate Waveforms

We are proposing a method for detecting bond wire lift-off, which is one of the causes of power device failure, by using machine learning of the gate voltage waveform of the power device. Compared with the conventional detection method, the detection circuit does not need to be isolated, and by applying a linear regression algorithm to the parameters extracted from the gate voltage waveform, we constructed a bond wire lift-off detection method that is robust to load current and temperature fluctuations.

Hybrid DC-DC Converter that Overcomes Trade-off between Efficiency and Volume

We are engaged in research and development of hybrid DC-DC converters that overcome the trade-off between efficiency and volume in conventional power supply circuits. In particular, we are focusing on applications with high input voltage and high step-down ratio power converters and are working on the development of circuit design technology by proposing a new circuit topology that reduces loss and cost by mixing inductors and flying capacitors.

Wireless Power Transfer System with Adaptive Magnetic Field Adder IC Integrating Shared Coupling Coefficient Sensor

To achieve a misalignment-free wireless power transfer (WPT), an IC for an adaptive magnetic field adder (AMFA), where the magnetic fields from multiple transmitter (TX) coils are adaptively added based on the coupling coefficient (k) between each TX coil and the receiver (RX) coil, is realized for the first time. A 6.78 MHz AMFA IC fabricated in 1.8 V, 180 nm CMOS integrating four power amplifiers and shared k sensor increases the perpendicular WPT efficiency from 0.02 % to 48.2 % with the load power of 458 mW.

Energy Efficient Near-Pixel 2D CNN Accelerator

The biggest issue in spreading AI technology widely in society is large power consumption. In particular, the power consumption of image recognition using a deep convolutional neural network (CNN) is quite large. For performing image recognition with high energy efficiency, the convolutional operation is performed only near the pixel of interest, which is the original feature of the CNN algorithm, and the digital circuit integrated near the pixel is used to achieve 2D CNN operation without writing data to an external memory.